US government announces first CHIPS Act research and development beneficiaries — $300 million awarded to three R&D facilities

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US government announces first CHIPS Act research and development beneficiaries — $300 million awarded to three R&D facilities

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the selection process for the first three CHIPS and Science Act research and development (R&D) facilities. The government has already earmarked billions of dollars for semiconductor manufacturers like Intel, Samsung, and TSMC. However, part of the bill includes funding for R&D facilities, and the U.S. government is now preparing to make those awards.

The announcement was co-authored by the U.S. Department of Commerce and Natcast, the National Semiconductor Technology Center (NTSC) operator. The idea here is to help “bridge the gap between research and industry.” Secretary of Commerce Gina Raimondo said that for the U.S. to reclaim a semiconductor leadership position, “we can’t just invest in manufacturing capacity, we also need to supercharge our research and development ecosystem.”

The planned CHIPS Act R&D facilities will help make that happen. The Act includes up to $11 billion for research and development, and the government intends to award up to $300 million for the first R&D facilities.

Funding will go towards three R&D centers: an NSTC Prototyping and National Advanced Packaging Manufacturing Program (NAPMP) Advanced Packaging Piloting Facility, an NSTC Administrative and Design Facility, and an NSTC Extreme Ultraviolet (EUV) Center.

Once up and running, the R&D facilities will help revitalize semiconductor research and development, addressing what government officials call “critical gaps in the current ecosystem.” Taiwan-based TSMC and Korea’s Samsung have led the charge in most recent semiconductor developments, with U.S.-based Micron contributing to the advances but not as prolifically as foreign-owned manufacturers.

The NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility will offer state-of-the-art manufacturing and packaging services. This R&D facility will also provide next-generation technology development. NSTC members and NAPMP-funded researchers will be able to conduct 300mm research, prototyping, and packaging. By co-locating the NSTC’s research and development prototyping and NAPMP’s packaging capabilities in one facility, the facility will offer a unique value in collaborative semiconductor and advanced packaging research to the U.S. semiconductor ecosystem.

The NSTC Administrative and Design Facility will be a multi-functional hub for the NSTC’s critical operations. It will host administrative functions and bring consortium members together. The facility will support various NSTC programs, including the Workforce Center of Excellence and the NSTC Design Enablement Gateway. The complex will also allow for advanced semiconductor research in chip design, electronic design automation, chip and system architecture, and hardware security.

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The NSTC EUV Center will provide NSTC members with access to EUV technology, which is essential for a wide range of research and advancing towards commercialization. It is vital for technologies with the most challenging feature sizes. This center will offer access to EUV lithography and space for Natcast researchers, staff, and member assignees to conduct research and collaborate.

Beginning July 15, the Department of Commerce and Natcast will issue a questionnaire for U.S. states and territories to help guide the selection of sites for the R&D facilities. Economic Development Organizations of all 56 states, territories, and the District of Columbia will be notified when the questionnaire is live and will have one week to complete it.

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