TSMC’s says 1.6nm node to be production ready in late 2026 — roadmap remains on track

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TSMC’s says 1.6nm node to be production ready in late 2026 — roadmap ******** on track

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Credit: TSMC

TSMC’s plans for the next couple of years remain largely unchanged as the company is ready to mass produce chips on its N2 (2nm-class) manufacturing technology starting in late 2025 and A16 (1.6nm-class) fabrication process in late 2026, the company announced at its Open Innovation Platform (OIP) 2024 conference here in Amsterdam, the Netherlands.

“The roadmap you see here is pretty much the same, actually it is the same technology roadmap that I think you saw during the [technology] symposium six months ago,” said Dan Kochpatcharin, Head of Design Infrastructure Management at TSMC. “[…] We have N2, N2P, which is coming [to] productions next year and the year after. And then [they are] followed by A16.”

The words ‘followed’ and the slide showing A16 after N2P and N2X was somewhat confusing to me. On the one hand, the slide TSMC shared is very similar to the one it presented back in May. On the other hand, the message sent back then was that A16, N2P, and N2X would be available around the same time, so I asked TSMC’s heads of the PR department to clarify.

TSMC

Indeed, all of these process technologies are slated to be ready for high volume manufacturing (HVM) in late 2026. This is, of course, as far as TSMC would go in official comments, as the company will not pre-announce products for its alpha customer(s) that are set to arrive on the market sometime in 2027. So, let us speculate about the positioning of these manufacturing processes.

Technically, N2, N2P, N2X, and A16 share many similarities: they are all based on nanosheet gate-all-around (GAA) transistors. The N2-series uses super-high-performance metal-insulator-metal (SHPMIM) capacitors to reduce transistor via resistance to improve performance efficiency, whereas A16 uses a backside power delivery network (BSPDN) to improve it even further.

“A16 is basically N2P [with the] the Super Power [Rail], which is our innovative backside power [delivery network],” said Dan Kochpatcharin.

While, generally, a BSPDN enables higher performance and better power efficiency, ‘there is no free lunch’ here, as noted by Ken Wang, TSMC’s Director of Design Solution Exploration. Backside power delivery also adds thermal issues that have to be mitigated. For now, a BSPDN in its current implementation is the best fit for datacenter-grade AI-aimed processors, a market segment that TSMC aims at with its A16 for now.

As for N2P, it enhances performance over typical N2 without adding complexities associated with a backside power delivery, which is optimal for client devices, such as system-on-chips (SoCs) for smartphones and entry-level PCs. N2X, of course, further enhances performance by adding higher voltages, which might be a benefit for a variety of applications, such as high-performance CPUs.

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